Semiconductor integrated circuit and method of allocating codes

ABSTRACT

A semiconductor integrated circuit includes a plurality of terminals, a first latch configured to, upon being uniquely specified by a first predetermined number of bits that are part of a plurality of bits entered through the terminals, store a second predetermined number of bits that are at least part of remaining bits left after excluding the first predetermined number of bits from the plurality of bits, and a second latch configured to, upon being uniquely specified by a third predetermined number of bits that are part of the plurality of bits entered through the terminals, store a fourth predetermined number of bits that are at least part of remaining bits left after excluding the third predetermined number of bits from the plurality of bits, wherein the first predetermined number is different from the third predetermined number, and the second predetermined number is different from the fourth predetermined number.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2007-154220 filed on Jun.11, 2007, with the Japanese Patent Office, the entire contents of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosures herein generally relate to semiconductor integratedcircuits, and particularly relate to a semiconductor integrated circuitprovided with registers for setting codes that specify functions and amethod of allocating such codes.

2. Description of the Related Art

In semiconductor devices, generally, a code specifying a particularoperation is entered from an external source to cause a semiconductordevice to perform the operation specified by the entered code. In asemiconductor memory device, for example, a code specifying a testoperation is entered from outside by using all or part of the bits forsupplying address signals, thereby causing the semiconductor memorydevice to perform a test operation specified by the entered code.Japanese Patent Application Publication No. 07-312098 discloses thisart.

SUMMARY OF THE INVENTION

According to one embodiment, a semiconductor integrated circuit includesa plurality of terminals, a first latch configured to, upon beinguniquely specified by a first predetermined number of bits that are partof a plurality of bits entered through the plurality of terminals, storea second predetermined number of bits that are at least part ofremaining bits left after excluding the first predetermined number ofbits from the plurality of bits, and a second latch configured to, uponbeing uniquely specified by a third predetermined number of bits thatare part of the plurality of bits entered through the plurality ofterminals, store a fourth predetermined number of bits that are at leastpart of remaining bits left after excluding the third predeterminednumber of bits from the plurality of bits, wherein the firstpredetermined number is different from the third predetermined number,and the second predetermined number is different from the fourthpredetermined number.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings, in which:

FIG. 1 is a drawing showing an example of test functions of asemiconductor memory device and the relationships between optionsettings and code values;

FIG. 2 is a drawing showing an example of test functions of asemiconductor memory device and the relationships between optionsettings and code values;

FIG. 3 is a drawing showing an example of the configuration of asemiconductor memory device;

FIG. 4 is a drawing showing a signal input/output sequence for causingthe semiconductor memory device to perform a test operation;

FIG. 5A is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 7-bit code fordiscriminating different options provided in each function;

FIG. 5B is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 5-bit code fordiscriminating different options provided in each function;

FIG. 5C is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 3-bit code fordiscriminating different options provided in each function;

FIG. 5D is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 2-bit code fordiscriminating different options provided in each function;

FIG. 5E is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 0-bit code fordiscriminating different options provided in each function;

FIG. 6 is a drawing showing an example of the configuration of a testregister shown in FIG. 3 in the case where the code allocation schemeshown in FIGS. 5A through 5E are used;

FIG. 7 is a drawing showing an example of the configuration of a 2-bitlatch shown in FIG. 6;

FIG. 8 is a drawing showing an example of a test circuit that operatesaccording to test function settings and option settings;

FIG. 9 is a drawing showing another example of a test circuit thatoperates according to test function settings and option settings;

FIG. 10A is a flowchart showing an example of a code allocation method;

FIG. 10B is a flowchart showing an example of the code allocationmethod;

FIG. 10C is a flowchart showing an example of the code allocationmethod;

FIG. 11 is a table showing the groups and computed values determined byperforming the steps shown in FIG. 10A;

FIG. 12 is a drawing showing the allocation of each code area obtainedfor each group according to step S8 with respect to the example shown inFIG. 11;

FIG. 13 is a drawing showing the allocation of bit patterns for uniquelyidentifying all the groups according to step S9;

FIG. 14 is a drawing showing the allocation of Cex to groups havingsmall LenCodeRest according to step S10;

FIG. 15 is a drawing showing the same bit pattern for Cgroup that isreassigned to Group[3] and Group[5];

FIG. 16 is a drawing showing further allocation of Cex according to stepS10;

FIG. 17 is a drawing showing the reallocation of bit patterns after thereduction of numbers of bits for Cgroup according to step S12;

FIG. 18 is a drawing showing the state after moving the unallocated bitsof Cex to between Cmain and Csub according to step S13;

FIG. 19 is a drawing showing the state after performing the process ofstep S15;

FIG. 20 is a drawing showing the state after performing the process ofstep S16;

FIG. 21 is a drawing showing an example of allocation of terminals to a7-bit main code and a 7-bit sub-code;

FIG. 22 is a drawing showing an example of allocation of codes toterminals when a main code and a sub-code are entered in two steps;

FIG. 23 is a drawing showing a signal input/output sequence with respectto a semiconductor memory device in the case of the code allocationshown in FIG. 22;

FIG. 24 is a drawing showing the configuration of a test register in thecase of the code allocation shown in FIG. 21; and

FIG. 25 is a drawing showing the configuration of a test register in thecase of the code allocation shown in FIG. 22.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In specifying a desired operation by use of a code, a two step codeallocation scheme may be used that specifies a desired function andfurther specifies an option with respect to the specified function. Forexample, with respect to a test function that adjusts a word-lineactivation voltage of a semiconductor memory device, one of theavailable options is selected to specify the use of a default voltage,the use of a voltage that is 100-mV higher than the default voltage, orthe use of a voltage that is 100-mV lower than the default voltage. Theword-line activation voltage is then set to the selected voltage. A codethat specifies a test function is referred to as a main code, and a codethat specifies an option is referred to as a sub-code.

FIG. 1 is a drawing showing an example of test functions of asemiconductor memory device and the relationships between optionsettings and code values. In FIG. 1, VPPTrim indicates a test functionfor adjusting a word-line activation voltage VPP, VBBTrim indicating atest function for adjusting a back bias VBB of memory cells, VBLEQTrimindicating a test function for adjusting an equalize level, and VPLTrimindicating a test function for adjusting a plate potential of memorycells. VPP external supply, VBB external supply, etc., refer to testfunctions for applying respective voltages from an external source.Further, wl-saeTrim indicates a test function for adjusting asense-amplifier activation timing. Moreover, DQ Compression and BankCompression refer to functions for performing tests by compressing dataand address, respectively.

These test functions are specified by a main code (MainCode) assigned toaddress bits A03 through A00. The setting of a main code to “0001”, forexample, specifies the VBBTrim function.

An option for a test function is selected by use of a sub-code (SubCode)assigned to address bits A06 through A04. For example, the VBBTrimfunction is specified by the main code “0001”, and, then, the back biasVBB is set to a default voltage by setting the sub-code to “000”. If thesub-code is set to “001”, for example, the back bias VBB is set to avoltage that is 100-mV higher than the default voltage.

The setting of test function and option as described above is performedwith respect to test registers provided in a semiconductor memory devicein accordance with entered main code and sub-code. Specifically, latches(registers) are provided in one-to-one correspondence to test functions.When a main code specifying a test function and a sub-code specifying anoption are entered, the latch specified by decoding the entered maincode stores the value of the entered sub-code. With such hardwareconfiguration, two or more test functions can simultaneously be selectedwhile preventing more than one option to be specified with respect toany test function.

In semiconductor devices, the numbers of input/output pins are limited.It is thus inevitable that the number of pins assignable to theabove-described main code and sub-code is limited. In the case of anSDRAM for which RAS/CAS addresses are multiplexed, the number of addressterminals is 12 if the column address is 8 bits and the row address is12 bits. Assuming that 2 terminals are already used for the purpose ofselecting a test mode and specifying the entry/exit of test mode, only10 terminals can be used for the purpose of specifying the codes.

When the number of terminals available for specifying codes is limitedas in this case, it becomes difficult to provide a desired number oftest functions and a desired number of options. If 64 different optionsare provided for a given test function, 6 bits need to be assigned forthe purpose of specifying a sub-code. In this case, the number ofremaining bits (terminals) available for allocation to a main code is 4.Namely, up to 16 test functions can only be specified.

Accordingly, there is a need for a method of allocating codes that canspecify as many functions as possible and as many options as possiblewithin the limitations posed by the limited number of bits. There isalso a need for an semiconductor integrated circuit that has settingregisters having hardware configuration suitable for such codeallocation.

In the following, embodiments of the present invention will be describedwith reference to the accompanying drawings. The present invention willbe described by using an example in which a test function is set for asemiconductor memory device. Nonetheless, the present invention is notlimited to the setting of test function with respect to a semiconductormemory device. It should be noted that the present invention isapplicable to setting of any operation and/or function by use ofregisters with respect to a semiconductor integrated circuit.

FIG. 2 is a drawing showing an example of test functions of asemiconductor memory device and the relationships between optionsettings and code values. In FIG. 2, test functions such as VPPTrim arethe same as those described in connection with FIG. 1. A test functionis specified by a main code (MainCode), and an option for a testfunction is specified by a sub-code (SubCode). The number of bits of themain code and the number of bits of the sub-code are designed to varyand be different for different functions according to need. With suchvariation in the number of bits of the main code and the number of bitsof the sub-code, a relatively small number of bits are sufficient tospecify a desired number of test functions and a desired number ofoptions.

The setting of address bits A04 through A00 to “00111”, for example,specifies the “+050 mV” option of the VBLEQTrim function. In this case,two bits A01 and A00 constitute a main code. The fact that these twobits are “11” uniquely identifies the VBLEQTrim function. Further, threebits A04 through A02 constitute a sub-code. The fact that these threebits are “001” uniquely identifies the “+050 mV” option. For theVBLEQTrim function, there are 8 different options, which require threebits for a sub-code to specify an option.

The setting of address bits A04 through A00 to “00101”, for example,specifies the default voltage option of the VPPTrim function. In thiscase, three bits A02 through A00 constitute a main code. The fact thatthese three bits are “101” uniquely identifies the VPPTrim function.Further, two bits A04 through A03 constitute a sub-code. The fact thatthese two bits are “00” uniquely identifies the default voltage option.For the VPPTrim function, there are 4 different options, which require 2bits for a sub-code to specify an option.

The setting of address bits A04 through A00 to “11110”, for example,specifies the VPP external supply function. In this case, all the fivebits A04 through A00 constitute a main code. The fact that these fivebits are “11110” uniquely identifies the VPP external supply function.For the VPP external supply function, no different options are provided(there is only one option), which require 0 bit for a sub-code tospecify an option.

In the case of the related-art code allocation scheme shown in FIG. 1,seven bits A00 through A06 are used as codes. In the case of the codeallocation scheme shown in FIG. 2, on the other hand, five bits A00through A04 are used as codes. The code allocation scheme shown in FIG.2 uses only five bits as codes, yet is able to specify as many testfunctions and options as there are in the related art allocation schemethat uses seven bits. A method of allocating codes that achieves suchcode allocation will later be described in detail.

The setting of test function and option as described above is performedwith respect to test registers provided in a semiconductor memory devicein accordance with entered main code and sub-code. Specifically, latches(registers) are provided in one-to-one correspondence to test functions.When a main code specifying a test function and a sub-code specifying anoption are entered, the latch specified by decoding the entered maincode stores the value of the entered sub-code. With such hardwareconfiguration, two or more test functions can simultaneously be selectedwhile preventing more than one option to be specified with respect toany test function.

In an example shown in FIG. 2, a first latch (i.e., the latch for theVBLEQTrim function), upon being specified by a first predeterminednumber of bits (two bits A01 and A00) that are part of a plurality ofbits entered through a plurality of terminals (address terminals A04through A00), stores a second predetermined number of bits (three bitsA04 through A02) that are at least part of the remaining bits (A04through A02) left after excluding the first predetermined number of bitsfrom the plurality of bits. Further, a second latch (i.e., the latch forthe VPPTrim function), upon being specified by a third predeterminednumber of bits (three bits A02 through A00) that are part of theplurality of bits entered through the plurality of terminals (addressterminals A04 through A00), stores a fourth predetermined number of bits(two bits A04 through A03) that are at least part of the remaining bits(A04 through A03) left after excluding the third predetermined number ofbits from the plurality of bits. Here, the first predetermined number(i.e., 2) is different from the third predetermined number (i.e., 3),and the second predetermined number (i.e., 3) is different from thefourth predetermined number (i.e., 2). The second predetermined numberof bits (i.e., A04 through A02) stored in the first latch (i.e., thelatch for the VBLEQTrim function) specifies an option for the VBLEQTrimfunction. Further, the fourth predetermined number of bits (i.e., A04through A03) stored in the second latch (i.e., the latch for the VPPTrimfunction) specifies an option for the VPPTrim function. Theconfiguration of such registers will later be described in detail.

FIG. 3 is a drawing showing an example of the configuration of asemiconductor memory device. A semiconductor memory device 10 shown inFIG. 3 includes a plurality of address terminals 11, a plurality ofother signal terminals 12, a plurality of buffers 13 corresponding torespective terminals, a pre-address control unit 14, a command controlunit 15, a timing control unit 16, a power generating unit 17, a testregister 18, a mode register 19, and banks 20 through 23. In FIG. 3,signal line connections between circuit components are illustrated onlyfor main connections for the sake of discernibility of illustratedparts.

The banks 20 through 23 all have the same configuration. Each of thebanks 20 through 23 includes, as shown in the bank 20 serving to berepresentative, a memory cell array 24, a row control unit 25, a columncontrol unit 26, a data bus switch 27, and an address control unit 28.

The plurality of address terminals 11 receive 12-bit address signalsA[11:0]. Here, X[y, z] represents the z-th bit to the y-th bit of asignal X. The signal terminals 12 serve to receive bank address BA[1:0],chip select CS, row address strobe RAS, column address strobe CAS, writeenable WE, a clock signal CLK, clock enable CKE, byte mask signalsDQM[1:0], data signals DQ[15:0], a power supply voltage VDD, a groundvoltage VSS, a stepped-up voltage VPP, and a back-bias voltage VBB. Thesignals or voltages applied to these terminals are supplied tocorresponding circuit parts via the buffers 13. The power supply voltageVDD, ground voltage VSS, stepped-up voltage VPP, and back-bias voltageVBB are directly supplied to the power generating unit 17 without theintervening buffers 13.

The command control unit 15 receive control signals comprised of thechip select CS, the row address strobe RAS, the column address strobeCAS, and the write enable WE. The command control unit 15 decodes thesecontrol signals to generate various control signals based on the decodedresults. These control signals are supplied to relevant circuit partssuch as the timing control unit 16, the test register 18, the moderegister 19, and so on. For example, the command control unit 15supplies, to the test register 18, a signal tespz indicating the loadingof test function and option settings to the registers. Further, thecommand control unit 15 supplies a signal mrspz indicating the settingof an operation mode such as a test mode to the mode register 19.

The timing control unit 16 generates various timing signalscorresponding to operations (e.g., data read operation, data writeoperation, and the like) specified by the control signals based on thecontrol signals from the command control unit 15, the clock signal CLK,and the clock enable signal CKE. The generated timing signals aresupplied to the banks 20 through 23, for example. Each circuit partoperates in accordance with the timings specified by these timingsignals.

The pre-address control unit 14 receives the bank address BA[1:0] andaddress signals A[11:0]. The pre-address control unit 14 specifies oneof the banks 20 through 23 according to the results obtained by decodingthe bank address BA[1:0]. Further, the pre-address control unit 14supplies address signals grax[11:0] having the same logic levels as theaddress signals A[11:0] to the test register 18, the mode register 19,and the banks 20 through 23.

The power generating unit 17 generates the stepped-up potential VPP byusing a stepping-up circuit based on the power supply potential VDD andthe ground potential VSS, and also generates the back-bias potential VBBby using a negative-voltage generating circuit. The stepped-up potentialVPP is used as a word-line activation potential, and the back-biaspotential VBB is used as a back bias in the circuit portion constitutingthe memory cell array. VPP and VBB that are externally supplied in FIG.3 are voltages applied from an external source when the VPP externalsupply function and the VBB external supply function are specified,respectively. The power generating unit 17 is further configured tocontrol an equalize level VBLEQ, a memory-cell plate potential VPL, andthe like in test operations.

In the memory cell array 24, a plurality of memory cells are arranged ina matrix form extending in a row direction and a column direction toconstitute a cell array. Each memory cell stores data. The memory cellarray 24 includes a plurality of word lines corresponding to a pluralityof row addresses, and a plurality of memory cells are coupled to eachword line. A plurality of bits lines are arranged in a direction inwhich column addresses are arranged, and sense amplifiers are coupled tothe respective bit lines.

The row control unit 25 decodes a row address supplied from thepre-address control unit 14 via the address control unit 28, andactivates a word line specified by the row address. The column controlunit 26 decodes a column address supplied from the pre-address controlunit 14 via the address control unit 28, and activates a columnselecting line specified by the column address.

Data stored in memory cells connected to an activated word line are readto the bit lines and amplified by the sense amplifiers. In the case ofread operation, the data amplified by the sense amplifiers is subjectedto selection by an activated column selecting line, and the selecteddata is output to outside the semiconductor memory device from the DQsignal terminals 12 via the data bus switch 27. In the case of writeoperation, write data is supplied from an external source outside thesemiconductor memory device via the DQ signal terminals 12 and the databus switch 27, and is written to sense amplifiers at the column addressselected by an activated column selecting line. This write data and thedata that were read from memory cells and ought to be restored arewritten to the memory cells connected to an activated word line.

FIG. 4 is a drawing showing a signal input/output sequence for causingthe semiconductor memory device 10 to perform a test operation. At thefirst clock cycle (01), CS, RAS, CAS, and WE are all set to LOW to entera register setting command MRS. At the same time, the address signalsA[11:0] supplied to the address terminals 11 are used to specify a code,thereby specifying a test function and an option. CS, RAS, CAS, and WEare then set to L, L, H, and H to enter an activation command ACT. Atthe same time, a bank address abnk and a row address aact are supplied.Thereafter, CS, RAS, CAS, and WE are set to L, H, L, and L to enter awrite command WR. At the same time, a bank address abnk, a columnaddress awr, and a write data dwr are supplied. Through the operationdescribed above, test-purpose data is written to the specified address.Finally, CS, RAS, CAS, and WE are set to L, L, H, and L to enter aprecharge command PRE. Through the operations described above, thewriting of test-purpose data to the specified address is completed.

At the sixth clock cycle (06), CS, RAS, CAS, and WE are all set to LOWto enter a register setting command MRS. At the same time, the addresssignals A[11:0] supplied to the address terminals 11 are used to specifyanother code (code2) different from the previous code, therebyspecifying a test function and an option. CS, RAS, CAS, and WE are thenset to L, L, H, and H to enter an activation command ACT. At the sametime, a bank address abnk and a row address aact are supplied. CS, RAS,CAS, and WE are then set to L, H, L, and H to enter a read command RD.At the same time, a bank address abnk and a column address awr aresupplied. Finally, CS, RAS, CAS, and WE are set to L, L, H, and L toenter a precharge command PRE. Read data drd is read after the passageof a predetermined latency following the read command. Through theoperations described above, the reading of the test-purpose data fromthe specified address is completed.

In the data writing and data reading operations described above, desiredoperating conditions are set by specifying test functions and options.For example, a word-line activation potential for use in the write andread operations is set to a specified potential to check whether datawriting and data reading are correctly performed. Alternatively, a senseamplifier activation timing in the write and read operations isadjusted, for example, to check whether data writing and data readingare correctly performed.

In the operations described above, the supply of the register settingcommand MRS entered by setting CS, RAS, CAS, and WE to LOW causes thecommand control unit 15 to assert a signal tespz shown in FIG. 3. Inresponse to the assertion of the signal tespz, the test register 18shown in FIG. 3 sets internal registers in accordance with the addresssignals grax[11:0] having the same logic levels as the address signalsA[11:0]. Thereafter, each circuit part operates in accordance withsignals tesz[0:128] and tsaz output in response to the internal registersettings of the test register 18, so that the voltage generated by thepower generating unit 17 may be adjusted, and/or the sense amplifieractivation timing specified by the timing control unit 16 may beadjusted. Voltages directly applied from an external source may as wellbe used.

In the semiconductor memory device 10 shown in FIG. 3, the addresssignals A[11:0] applied to the address terminals 11 are used to specifytest functions and options. In the following example, allocation ofcodes to the address signals A[11:0] will be described with reference toa case in which there are 2 functions requiring a 7-bit code forspecifying one of the different options provided for each function, 8functions requiring a 5-bit code for specifying one of the differentoptions provided for each function, 16 functions requiring a 3-bit codefor specifying one of the different options provided for each function,16 functions requiring a 2-bit code for specifying one of the differentoptions provided for each function, and 32 functions requiring a 0-bitcode for specifying one of the different options provided for eachfunction. In this case, a total of 74 (=2+8+16+16+32) functions areprovided.

It should be noted that an address signal A08 is already assigned to beset to “1” when using a mode register set MRS for setting a testoperation mode in the mode register 19. Namely, the address signal A08is reserved for the mode register set MRS, and cannot be used for thepurpose of allocating codes. Further, an address signal A07 is alreadyassigned to be set to “1” when entering a test operation mode and to beset to “0” when exiting from a test operation mode. Namely, the addresssignal A07 is reserved for specifying entering/exiting into/from a testoperation, and cannot be used for the purpose of allocating codes.

FIG. 5A is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 7-bit code fordiscriminating different options provided in each function. Since 7 bitsare necessary to discriminate different options provided in eachfunction, a sub-code requires 7 bits. In this case, 7 bits A06 throughA00 are allocated for use as a sub-code (“Sub”). Further, three bits A11through A09 are allocated for use as a main code. In FIG. 5A, the maincode is denoted as a group code (“Group”). Here, the group code refersto a portion of a main code that is used to discriminate groups intowhich functions having sub-codes comprised of the same number of bitsare grouped. In this example, there are a total of 5 groups, including agroup having 7-bit sub-codes, a group having 5-bit sub-codes, a grouphaving 3-bit sub-codes, a group having 2-bit sub-codes, and a grouphaving 0-bit sub-codes. Three bits are required to discriminate these 5groups, so that 3 bits are allocated for use a group code.

The group having 7-bit sub-codes is specified by the group code A11through A09 being “11x” (x: don't care). There are 2 different functionsin the group having 7-bit sub-codes. In order to discriminate these twofunctions, A09 that is part of the group code may be used.

FIG. 5B is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 5-bit code fordiscriminating different options provided in each function. Since 5 bitsare necessary to discriminate different options provided in eachfunction, a sub-code requires 5 bits. In this case, 5 bits A06 throughA02 are allocated for use as a sub-code (“Sub”). Further, three bits A11through A09 and two bits A01 and A00, which are 5 bits in total, areallocated for use as a main code. Among these 5 bits, three bits A11through A09 are allocated for use as a group code (“Group”).

The group having 5-bit sub-codes is specified by the group code A11through A09 being “10x” (x: don't care). There are 8 different functionsin the group having 5-bit sub-codes. In order to discriminate these 8functions, A09 that is part of the group code and the remaining bits A01and A00 of the main code, which are 3 bits in total, may be used.

FIG. 5C is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 3-bit code fordiscriminating different options provided in each function. Since 3 bitsare necessary to discriminate different options provided in eachfunction, a sub-code requires 3 bits. In this case, 3 bits A06 throughA04 are allocated for use as a sub-code (“Sub”). Further, three bits A11through A09 and four bits A03 through A00, which are 7 bits in total,are allocated for use as a main code. Among these 7 bits, three bits A11through A09 are allocated for use as a group code (“Group”).

The group having 3-bit sub-codes is specified by the group code A11through A09 being “100”. There are 16 different functions in the grouphaving 3-bit sub-codes. In order to discriminate these 16 functions, theremaining bits A03 through A00 of the main code left after excluding thegroup code, which are 4 bits in total, are used.

FIG. 5D is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 2-bit code fordiscriminating different options provided in each function. Since 2 bitsare necessary to discriminate different options provided in eachfunction, a sub-code requires 2 bits. In this case, 2 bits A06 and A05are allocated for use as a sub-code (“Sub”). Further, three bits A11through A09 and four bits A03 through A00, which are 7 bits in total,are allocated for use as a main code. Among these 7 bits, three bits A11through A09 are allocated for use as a group code (“Group”).

The group having 2-bit sub-codes is specified by the group code A11through A09 being “011”. There are 16 different functions in the grouphaving 2-bit sub-codes. In order to discriminate these 16 functions, theremaining bits A03 through A00 of the main code left after excluding thegroup code, which are 4 bits in total, are used. In this case, bit A04is not necessary, and is not used.

FIG. 5E is a drawing showing an example of allocation of a main code andsub-code with respect to a function requiring a 0-bit code fordiscriminating different options provided in each function. Since 0 bitsare necessary to discriminate different options provided in eachfunction, a sub-code requires 0 bits. In this case, no bit is allocatedfor a sub-code. Further, three bits A11 through A09 and four bits A03through A00, which are 7 bits in total, are allocated for use as a maincode. Among these 7 bits, three bits A11 through A09 are allocated foruse as a group code (“Group”).

The group having 0-bit sub-codes is specified by the group code A11through A09 being “00x” (x: don't care). There are 32 differentfunctions in the group having 0-bit sub-codes. In order to discriminatethese 32 functions, A09 that is part of the group code and the remainingbits A03 through A00 of the main code, which are 5 bits in total, areused. In this case, bits A06 through A04 are not necessary, and are notused.

FIG. 6 is a drawing showing an example of the configuration of the testregister 18 shown in FIG. 3 in the case where the code allocation schemeshown in FIGS. 5A through 5E are used. In FIG. 6, the test register 18includes a latch control unit 31, a decoder 32, a decoder 33, a groupdecoder 34, a 7-bit latch 35, a 5-bit latch 36, a 3-bit latch 37, a2-bit latch 38, and a 0-bit latch 39.

The address signals A00 through A11 shown in FIGS. 5A through 5Ecorrespond to the address signals grax[00:11]. It should be noted that asignal with a signal name ending with “z” is positive logic, and asignal with a signal name ending with “x” is negative logic. The addresssignals grax[00:11] are supplied as negative logic signals. In responseto grax[07:08] and the signal tespz, the latch control unit 31 generatesa signal tentz requesting the setting of each latch and a signal texitzrequesting the resetting of each latch. In response to the assertion ofgrax[07] (i.e., 1 bit of the signal grax specified by “07”) to “0”, thelatch control unit 31 sets the signal tentz to HIGH. In response to thenegation of grax[07] (i.e., 1 bit of the signal grax specified by “07”)to “1”, the latch control unit 31 sets the signal texitz to HIGH.

The decoder 32 decodes grax[00:01] that is part of the main code toproduce a decode signal taax[0:3]. The decoder 33 decodes grax[02:03]that is part of the main code to produce a decode signal tabx[0:3]. Thereason why the decoder 32 and the decoder 33 are provided as separatecircuits is that while A00 through A03 are main codes in FIGS. 5Cthrough 5E, A00 and A01 are a main code and A02 and A03 are a sub-codein the case of FIG. 5B. The decoder 32 is responsible for the decodingof A00 and A01 while the decoder 33 is responsible for the decoding ofA02 and A03. The group decoder 34 decodes grax[09:11] that is a groupcode to produce a decode signal grpx[0:7]. The decode signals producedby these decoders uniquely specify one of the provided latches.

For the sake of simplicity of illustration, only one 7-bit latch 35 thatreceives decode signal grpx[7] is illustrated in FIG. 6. In reality,however, two 7-bit latches 35 are provided in one-to-one correspondenceto two functions, one of which receives grpx[7] and the other receivesgrpx[6]. grpx[7] is asserted in the case of the group code A11 throughA09 being “111”, and grpx[6] is asserted in the case of the group codeA11 through A09 being “110”. In this manner, the use of A09 that is partof the group code makes it possible to discriminate 2 differentfunctions.

When one 7-bit latch 35 is uniquely specified by the decode signals,this specified 7-bit latch 35 stores (latches) the value of grax[00:06]that is a sub-code. Upon the setting of the value, output tes7#z of this7-bit latch 35 is asserted to HIGH, and, also, output tsa7#z[0:6] thatis logically inverse to grax[00:06] is output. The assertion of tes7#zindicates that the outputs of the 7-bit latch 35 are valid, so that theoutput tsa7#z[00:06] can specify what the option setting is. Here, “#”appearing in a signal name is a symbol for discriminating two 7-bitlatches 35 provided for the two respective functions, and assumes “0” or“1” depending on which function is referred to.

The 7-bit latch 35 receives the decode signal only from the groupdecoder 34, and does not receive any decode signals from the decoder 32or the decoder 33. In order to allow visualization of signal paths thatare not conveying signals, the position of signal lines that are not inexistence in reality are shown by dotted lines. The reason why thesignal lines shown by dotted lines are not in existence is that thefunctions requiring 7-bit sub-codes can be specified by using only agroup code as shown in FIG. 5A. The absence of the signal paths shown bydotted lines significantly reduces the number of signal lines in thetest register 18 compared with conventional configurations.

By the same token, only one 5-bit latch 36 that receives decode signalgrpx[5] is illustrated in FIG. 6. In reality, however, eight 5-bitlatches 36 are provided in one-to-one correspondence to eight functions,four of which receive grpx[5] and the remaining four receive grpx[4].grpx[5] is asserted in the case of the group code A11 through A09 being“101”, and grpx[4] is asserted in the case of the group code A11 throughA09 being “100”. The assertion of one of the two signals causesselection of either the first four 5-bit latches 36 or the second four5-bit latches 36. In order to uniquely specify one of the four selected5-bit latches 36, each bit taax of decode output taax[0:3] of thedecoder 32 is supplied to a corresponding one of the 5-bit latches 36.This makes it possible to specify one function.

When one 5-bit latch 36 is uniquely specified by the decode signals,this specified 5-bit latch 36 stores (latches) the value of grax[02:06]that is a sub-code. Upon the setting of the value, output tes5#z of this5-bit latch 36 is asserted to HIGH, and, also, output tsa5#z[2:6] thatis logically inverse to grax[02:06] is output. The assertion of tes5#zindicates that the outputs of the 5-bit latch 36 are valid, so that theoutput tsa5#z[2:6] can specify what the option setting is. Here, “#”appearing in a signal name is a symbol for discriminating eight 5-bitlatches 36 provided for the eight respective functions, and assumes oneof “0” through “7” depending on which one of the eight functions isreferred to.

The 5-bit latch 36 receives the decode signals only from the groupdecoder 34 and the decoder 32, and does not receive any decode signalsfrom the decoder 33. In order to allow visualization of signal pathsthat are not conveying signals, the position of signal lines that arenot in existence in reality are shown by dotted lines. The reason whythe signal lines shown by dotted lines are not in existence is that thefunctions requiring 5-bit sub-codes can be specified by using only agroup code and AO to A1 as shown in FIG. 5B. The absence of the signalpaths shown by dotted lines significantly reduces the number of signallines in the test register 18 compared with conventional configurations.

As for 3-bit latches 37, sixteen 3-bit latches 37 are provided inone-to-one correspondence to the 16 functions. Each 3-bit latch 37receives decode signal grpx[3]. The assertion of decode signal grpx[3]causes the sixteen 3-bit latches 37 to be selected among all the latchesshown in FIG. 6. In order to uniquely specify one of the sixteenselected 3-bit latches 37, each bit taax of decode output taax[0:3] ofthe decoder 32 and each bit tabx of decode output tabx[0:3] of thedecoder 33 are used. The specified one of the 3-bit latches 37 stores(latches) the value of grax[04:06] that is a sub-code. The roles of theoutputs of the 3-bit latch 37 are the same as those of the outputs ofthe 7-bit latch 35 and the 5-bit latch 36 as previously described.

As for 2-bit latches 38, sixteen 2-bit latches 38 are provided inone-to-one correspondence to the 16 functions. Each 2-bit latch 38receives decode signal grpx[2]. The assertion of decode signal grpx[2]causes the sixteen 2-bit latches 38 to be selected among all the latchesshown in FIG. 6. In order to uniquely specify one of the sixteenselected 2-bit latches 38, each bit taax of decode output taax[0:3] ofthe decoder 32 and each bit tabx of decode output tabx[0:3] of thedecoder 33 are used. The specified one of the 2-bit latches 38 stores(latches) the value of grax[05:06] that is a sub-code. The roles of theoutputs of the 2-bit latch 38 are the same as those of the outputs ofthe 7-bit latch 35 and the 5-bit latch 36 as previously described.

As for 0-bit latches 39, thirty-two 0-bit latches 39 are provided inone-to-one correspondence to the 32 functions. Sixteen of them receivegrpx[0], and the remaining sixteen receive grpx[1]. grpx[1] is assertedin the case of the group code A11 through A09 being “001”, and grpx[0]is asserted in the case of the group code A11 through A09 being “000”.The assertion of one of the two signals causes selection of either thefirst sixteen 0-bit latches 39 or the second sixteen 0-bit latches 39.In order to uniquely specify one of the sixteen selected 0-bit latches39, each bit taax of decode output taax[0:3] of the decoder 32 and eachbit tabx of decode output tabx[0:3] of the decoder 33 are used. Thespecified one of the 0-bit latches 39 does not latch the sub-code, butasserts its output tes0#z to indicate that the latch has been specified.Here, “#” appearing in a signal name is a symbol for discriminatingthirty-two 0-bit latches 39 provided for the 32 respective functions,and assumes one of “0” through “31” depending on which one of the 32functions is referred to.

In the manner as described above, the decode outputs of the decoder 32,the decoder 33, and the group decoder 34 are used to uniquely specifyone latch (i.e., one function) with respect to the 3-bit latches 37, the2-bit latches 38, and the 0-bit latches 39.

FIG. 7 is a drawing showing an example of the configuration of the 2-bitlatch 38 shown in FIG. 6. The 2-bit latch 38 shown in FIG. 7 includes aNOR gate 40, a NAND gate 41, a NAND gate 42, an inverter 43, two latchcircuits 44, and a latch circuit 45. The two latch circuits 44 and thelatch circuit 45 all have the same configuration, and each include aninverter 50, a transfer gate 51 comprised of a PMOS transistor and anNMOS transistor, a NAND gate 52, an inverter 53, and an inverter 54.

One bit taax of the decode signals taax[0:3] output from the decoder 32,one bit tabx of the decode signals tabx[0:3] output from the decoder 33,and one bit grpx (=grpx[2]) of the decode signals grpx[0:7] output fromthe group decoder 34 are supplied to the NOR gate 40. When all thesethree inputs are asserted to “0”, the 2-bit latch 38 shown in FIG. 7 isuniquely specified, so that the output of the NOR gate 40 becomes HIGH.At the time of register setting, texitz is set to LOW, and tentz is setto HIGH. Accordingly, the output of the NAND gate 42 is set to LOW, sothat the transfer gate 51 becomes conductive in each of the latchcircuits 44 and 45. As a result, the two latch circuits 44 store twobits grax [06:05], so that the output signals tsa2#z are logicallyinverse to grax[06:05]. Further, the latch circuit 45 stores the groundpotential LOW, so that the output signal tes2#z becomes HIGH that islogically inverse to LOW.

At the time of register resetting, texitz is set to HIGH, and tentz isset to LOW. Accordingly, the output of the NAND gate 41 is set to LOW,so that the output of the NAND gate 52 is set to HIGH in each of thelatch circuits 44 and 45. This causes all the outputs of the latchcircuits 44 and 45 to be set to LOW.

Only the configuration of the 2-bit latch 38 is shown in FIG. 7. The7-bit latch 35, 5-bit latch 36, 3-bit latch 37, and 0-bit latch 39 canbe configured similarly to the manner in which the 2-bit latch 38 isconfigured. In the case of the 0-bit latch 39, however, the latchcircuits 44 are not necessary, and only the latch circuit 45 isprovided.

FIG. 8 is a drawing showing an example of a test circuit that operatesaccording to test function settings and option settings. The testcircuit shown in FIG. 8 serves to provide a test function for adjustingsense amplifier activation timing, and may be provided in the timingcontrol unit 16 of the semiconductor memory device 10 shown in FIG. 3.

The test circuit shown in FIG. 8 includes a decoder 61 and delaycircuits 62 through 65. The delay circuits 62 through 65 all have thesame configuration, and each include an AND gate 70, a NAND gate 71, aninverter 72, a capacitor 73, a capacitor 74, a resistor 75, and aregister 76. The output signal of the NAND gate 71 propagates with somedelay through the signal propagation path comprised of the inverter 72,the capacitor 73, the capacitor 74, the resistor 75, and the register76.

The decoder 61 receives and decodes tsa20 z[0] and tsa20 z[1] outputfrom one 2-bit latch 38, and outputs the decode results as signalstwlsaez[0] through twlsaez[3]. In response to the specified option, oneof twlsaez[0] through twlsaez[3] becomes HIGH. When twlsaez[1] is set toHIGH, a HIGH pulse appears in the output of the AND gate 70 of the delaycircuit 63 in response to the HIGH pulse of the signal mwlonz requestingthe activation of a word line. In response, a LOW pulse appears in theoutput of the NAND gate 71. This LOW pulse propagates through the delaycircuits 63 through 65, and is output as a sense amplifier activationsignal msaeonz after the corresponding delay. The delay time of each oneof the delay circuits 62 through 65 is denoted as TD, and the senseamplifier activation signal msaeonz responsive to the assertion oftwlsaez[0] to HIGH is a default timing. Then, the assertion oftwlsaez[1] corresponds to the “+TD” option. The assertion of twlsaez[2]corresponds to the “+2TD” option. Further, the assertion of twlsaez[3]corresponds to the “−TD” option.

FIG. 9 is a drawing showing another example of a test circuit thatoperates according to test function settings and option settings. Thetest circuit shown in FIG. 9 serves to provide a test function foradjusting the stepped-up potential VPP, and may be provided in the powergenerating unit 17 of the semiconductor memory device 10 shown in FIG.3.

The test circuit shown in FIG. 9 includes a decoder 81, transfer gates82 through 85 each comprised of a PMOS transistor and an NMOStransistor, PMOS transistors 86 and 87, NMOS transistors 88 and 89, aninverter 91, a stepping-up circuit 92, and registers R1 through R5. ThePMOS transistors 86 and 87 and the NMOS transistors 88 and 89 constitutea differential amplifier.

The stepping-up circuit 92 operates in response to the assertion of astepping-up circuit activating signal vppupz to HIGH to generate thestepped-up potential VPP. The generated stepped-up potential VPP issupplied to an end of a potential divider comprised of series connectedresistors R1 through R5. Among a plurality of different potentialsgenerated by the potential divider dividing the stepped-up voltage VPP,a potential selected by one of the transfer gates 82 through 85 that ismade conductive is supplied as a divided potential nrvpp to thedifferential amplifier. When the divided potential nrvpp becomes higherthan a reference potential vref, the differential amplifier sets aninput into the inverter 91 to HIGH. In response, the stepping-up circuitactivating signal vppupz is negated to LOW. This causes the operation ofthe stepping-up circuit 92 to stop, thereby causing the stepped-uppotential VPP to drop. When the divided potential nrvpp becomes lowerthan the reference potential vref, on the other hand, the differentialamplifier sets the input into the inverter 91 to LOW. In response, thestepping-up circuit activating signal vppupz is asserted to HIGH. Thisactivates the stepping-up circuit 92, thereby causing the stepped-uppotential VPP to rise. Through this feedback control, the stepped-uppotential VPP is adjusted equal to a predetermined potential.

The decoder 81 receives and decodes tsa21 z[0] and tsa21 z[1] outputfrom one 2-bit latch 38, and outputs the decode results as signalstvpptrimz[0] through tvpptrimz[3]. In response to the specified option,one of tvpptrimz[0] through tvpptrimz[3] becomes HIGH. When tvpptrimz[3]is set to HIGH, for example, a voltage obtained by dividing thestepped-up voltage VPP according to (R3+R4+R5)/(R1+R2+R3+R4+R5) issupplied as a divided potential nrvpp to the differential amplifier. Inthis case, the stepped-up potential VPP is adjusted equal tovref·(R1+R2+R3+R4+R5)/(R3+R4+R5).

FIGS. 10A through 10C are flowcharts showing an example of a codeallocation method. In step S1, LenSub that is a bit length of a sub-codeassigned to each function is extracted (determined) with respect to eachfunction. In step S2, all the functions are grouped according to LenSub.

In step S3, group count CountGroup and function count CountMainindicative of the number of functions in each group are counted. In stepS4, LenCode[LenSub] indicative of the length of an entire code isestimated with respect to each group. The estimated length of an entirecode is a sum of the number of bits required to represent the number ofthe groups, the number of bits required to represent the functionsbelonging to each group, and the number of bits of the sub-code. Namely,LenCode is expressed as follows.

LenCode[LenSub]=Log₂(CountGroup)+Log₂(CountMain[LenSub])+LenSub

In step S5, an initial value of a code length (LenCodeUse) isdetermined. Here, the initial value of a code length is the largest ofestimated code lengths of entire codes (which differ with respect toeach group). Namely, the initial value of a code length is obtained asMax(LenCode[LenSub]).

In step S6, LenCodeRest indicative of the bit length of an unused codeportion in each group is obtained. Namely, LenCodeRest is obtained asfollows.

LenCodeRest=LenCodeUse−LenCode[LenSub]

In step S7, all the groups are sorted in the ascending order ofLenCodeRest.

FIG. 11 is a table showing the groups and computed values determined byperforming the steps shown in FIG. 10A. In the example shown in FIG. 11,there are 5 groups which have sub-codes of 7, 5, 3, 2, and 0 bits,respectively, with the respective numbers of functions being 2, 4, 14,13, and 32.

In step S8 shown in FIG. 10B that is performed after step S7 shown inFIG. 10A, code areas are allocated for Cgroup, Cex, Cmain, and Csub inthis order in each group, where Cex corresponds to the bits ofLenCodeRest. Here, Cgroup corresponds to the bit area of a group code,Cmain to the bit area of a main code (i.e., the portion of the main codeleft after excluding the group code), and Csub to the bit area of asub-code. Cex is an extension code.

FIG. 12 is a drawing showing the allocation of each code area obtainedfor each group according to step S8 with respect to the example shown inFIG. 11. The number of bits of Csub is equal to LenSub. The number ofbits of Cmain is equal to the number of bits required to represent thenumber of all the functions in each group. The number of bits of Cgroupis equal to the number of bits required to represent the number of allthe groups.

In this manner, LenSub that is the minimum number of bits capable ofuniquely identifying all the options for each function is determined(step S1) as the number of bits of a sub-code that uniquely identifiesan option for each function, followed by grouping the functions (stepS2) such that the functions with the sub-codes having the same number ofbits are grouped together, allocating the first bit area Csub (step S8)in the bit sequence C10 through COO of each group for a sub-codecomprised of a number of bits unique to each group, allocating thesecond bit area Cgroup (step S8) in the bit sequence C10 through COO fora group code capable of uniquely identifying all the groups, andallocating the third bit area Cmain (step S8) to the bit area allocatedto neither the first bit area nor the second bit area in the bitsequence for a main code for identifying a function in each group.

Referring to FIG. 10B again, in step S9, bit patterns for uniquelyidentifying the groups are assigned as Cgroup. FIG. 13 is a drawingshowing the allocation of bit patterns for uniquely identifying all thegroups according to step S9.

In step S10, Cex is allocated in the ascending order of LenCodeRest,and, then, the groups that can be uniquely identified by additional useof Cex are put together and reassigned with the same bit pattern forCgroup. In step S11, a check is made as to whether there are groups thatcan be integrated by allocating Cex. If the result of the check isaffirmative (Yes), the procedure goes back to step S10 to repeat thesubsequent steps.

FIG. 14 is a drawing showing the allocation of Cex to groups havingsmall LenCodeRest according to step S10. Cex=0 is allocated to Group[3],and Cex=1 is allocated to Group[5]. Since Group[3] and Group[5] can bediscriminated (i.e., uniquely identified) by use of an extension codeCex, Group[3] and Group[5] can be integrated. Accordingly, the same bitpattern for Cgroup is reassigned to Group[3] and Group[5].

FIG. 15 is a drawing showing the same bit pattern for Cgroup that isreassigned to Group[3] and Group[5]. The bit pattern “110” is assignedas Cgroup to Group[3] and Group[5].

FIG. 16 is a drawing showing further allocation of Cex according to stepS10. Cex=1x is allocated to Group [2], and Cex=0xx is allocated toGroup[0]. Since Group[2] and Group[0] can be discriminated (i.e.,uniquely identified) by use of an extension code Cex, Group[2] andGroup[0] can be integrated. Accordingly, the same bit pattern “100” forCgroup is reassigned to Group[2] and Group[0].

Referring to FIG. 10B again, in step S12, the number of bits of Cgroupis reduced and codes are reallocated to each group if the number of bitsrequired for Cgroup is reduced by step S10. FIG. 17 is a drawing showingthe reallocation of bit patterns after the reduction of numbers of bitsfor Cgroup according to step S12. From FIG. 16, it can be understoodthat there are only 3 groups after the integration of groups. It followsthat 2 bits are sufficient as the number of bits to represent Cgroup. InFIG. 17, therefore, the number of bits for Cgroup is reduced by one toreduce the bit length of the entire code by one bit. Bit patterns forCgroup are then reallocated. By repeating S9 through S12, it is possibleto obtain the minimum number of bits required for Cgroup.

In step S13, the bits that are not yet allocated in Cex are moved tobetween Cmain and Csub. FIG. 18 is a drawing showing the state aftermoving the unallocated bits of Cex to between Cmain and Csub accordingto step S13.

In step S14 shown in FIG. 10C, a check is made as to whether anyunallocated bit pattern exists for Cgroup. If there is an unallocatedbit pattern for Cgroup, one additional bit pattern for Cgroup isallocated in step S15 to the group having the longest total code lengthof Cex and Cmain, followed by removing 1 bit from Cmain.

FIG. 19 is a drawing showing the state after performing the process ofstep S15. In FIG. 18, the bit pattern “00” for Cgroup is not yetallocated. Accordingly, the bit pattern “00” for Cgroup is additionallyallocated to Group[0] having the longest total code length of Cex andCmain. Further, the number of bits for Cmain in Group[0] is reduced from5 to 4.

In step S16, Cgroup, Cex, and Cmain are put together, and boundaries arereassigned to achieve easy decoding. FIG. 20 is a drawing showing thestate after performing the process of step S16. In FIG. 20, C09 throughC07 are decoded by the group decoder, C06 and C05 by the first decoder,and C04 and C03 by the second decoder.

In step S17, finally, Cmain and Csub are allocated to each function.With this, the procedure for allocating codes comes to an end.

In order to provide an advantage over the allocation of fixed numbers ofbits to main codes and sub-codes as in the related-art configuration,the bit length of the third bit area Cmain for Group[7] having thelongest sub-code bit length is preferably shorter than the bit length ofthe third bit area Cmain for another group (e.g., Group[3]). Namely, itis preferable to have a smaller number of functions for a group having alarger number of options. In order to provide a further advantage, atleast one or more bit positions (e.g., C06 through C03) in the bitsequence C06 through C00 corresponding to the first bit area Csub forGroup[7] having the longest sub-code bit length are preferably allocatedto the third bit area Cmain in another group (e.g., Group[3]).

In the following, the advantages of the embodiments described above incomparison with the related-art configuration will be described. FIG. 21is a drawing showing the allocation of codes when the lengths of maincodes and sub-codes are fixed with respect to the test functions andoptions corresponding to the example shown in FIGS. 5A through 5E. Inthis example as previously described, there are 2 functions requiring a7-bit code for specifying one of the different options provided for eachfunction, 8 functions requiring a 5-bit code for specifying one of thedifferent options provided for each function, 16 functions requiring a3-bit code for specifying one of the different options provided for eachfunction, 16 functions requiring a 2-bit code for specifying one of thedifferent options provided for each function, and 32 functions requiringa 0-bit code for specifying one of the different options provided foreach function. Since the maximum number of bits required for the purposeof option identification is 7, 7 bits will be allocated for sub-codeshaving a fixed length. Further, there are 74 functions in total, so that7-bit main codes having a fixed length will be necessary for the purposeof uniquely identifying each function. As a result, 7-bit main codes and7-bit sub-codes are used.

FIG. 21 is a drawing showing an example of allocation of terminals to a7-bit main code and a 7-bit sub-code. In FIG. 21, address bits A00through A06 are allocated to the main code. The remaining availableaddress bits are A11 through A09, which are only 3 bits. There is thus aneed for 4 additional bits assigned for use as a sub-code. Terminals BA0and BA1 for bank address signals and extension-purpose terminals Ax0 andAx1, for example, may be used to provide 7 bits for use as a sub-code.In this case, 14 terminals are necessary, which is a significantincrease in the numbers of terminals, compared to the 10 terminalsnecessary in the previously-described embodiments.

FIG. 22 is a drawing showing an example of allocation of codes toterminals when a main code and a sub-code are entered in two steps. Inthe same manner as in the preceding case, 7-bit main codes and 7-bitsub-codes are used in this case. Since a main code and a sub-code aresupplied to the semiconductor memory device at separate timings, themain code and the sub-code can be allocated to the same terminals. Inthe example shown in FIG. 22, address bits A00 through A06 are allocatedto both the main code and the sub-code

FIG. 23 is a drawing showing a signal input/output sequence with respectto a semiconductor memory device in the case of the code allocationshown in FIG. 22. At the first clock cycle (01), CS, RAS, CAS, and WEare all set to LOW to enter a register setting command MRS. At the sametime, the address signals A[8:0] supplied to the address terminals 11are used to specify a main code (code1), thereby specifying a testfunction. Then, CS, RAS, CAS, and WE are all set to LOW to enter aregister setting command MRS. At the same time, the address signalsA[8:0] supplied to the address terminals 11 are used to specify asub-code (code2), thereby specifying an option.

CS, RAS, CAS, and WE are then set to L, L, H, and H to enter anactivation command ACT. At the same time, a bank address abnk and a rowaddress aact are supplied. Thereafter, CS, RAS, CAS, and WE are set toL, H, L, and L to enter a write command WR. At the same time, a bankaddress abnk, a column address awr, and a write data dwr are supplied.Through the operation described above, test-purpose data is written tothe specified address. Finally, CS, RAS, CAS, and WE are set to L, L, H,and L to enter a precharge command PRE. Through the operations describedabove, the writing of test-purpose data to the specified address iscompleted.

At the seventh clock cycle (07), CS, RAS, CAS, and WE are all set to LOWto enter a register setting command MRS. At the same time, the addresssignals A[8:0] supplied to the address terminals 11 are used to specifya main code (code1), thereby specifying a test function. Then, CS, RAS,CAS, and WE are all set to LOW to enter a register setting command MRS.At the same time, the address signals A[8:0] supplied to the addressterminals 11 are used to specify a sub-code (code2), thereby specifyingan option.

CS, RAS, CAS, and WE are then set to L, L, H, and H to enter anactivation command ACT. At the same time, a bank address abnk and a rowaddress aact are supplied. CS, RAS, CAS, and WE are then set to L, H, L,and H to enter a read command RD. At the same time, a bank address abnkand a column address awr are supplied. Finally, CS, RAS, CAS, and WE areset to L, L, H, and L to enter a precharge command PRE. Read data drd isread after the passage of a predetermined latency following the readcommand. Through the operations described above, the reading of thetest-purpose data from the specified address is completed.

When a main code and a sub-code are entered in two separate steps asdescribed above, one additional process cycle is necessary for each ofthe write operation and the read operation. In the case of the codeallocation as shown in FIG. 22, the number of required terminals isreduced, but the length of time required for test operation undesirablyincreases.

FIG. 24 is a drawing showing the configuration of a test register in thecase of the code allocation shown in FIG. 21. A test register shown inFIG. 24 includes a latch control unit 131, a decoder 132, a decoder 133,a group decoder 134, a 7-bit latch 135, a 5-bit latch 136, a 3-bit latch137, a 2-bit latch 138, and a 0-bit latch 139. Unlike the configurationshown in FIG. 6, the decode outputs of the decoders 132, 133, and 134are supplied to all the latches. This is because the main codes have afixed length of 7 bits, and the decode result obtained by decoding a7-bit main code is used to identify one of the latches. In this manner,the number of signal lines used in the test register is larger than thatof the configuration shown in FIG. 6.

FIG. 25 is a drawing showing the configuration of a test register in thecase of the code allocation shown in FIG. 22. A test register shown inFIG. 24 includes a latch control unit 131, a decoder 132, a decoder 133,a group decoder 134, a 7-bit latch 135, a 5-bit latch 136, a 3-bit latch137, a 2-bit latch 138, a 0-bit latch 139, and a shift register 140. Inthe case of the code allocation shown in FIG. 22, a main code and asub-code are supplied to the same terminals at separate timings, so thatthe shift register 140 is necessary to store the code that is suppliedfirst. In this case, the number of signal lines used in the testregister is larger than that of the configuration shown in FIG. 6, and,also, one additional register the same size as the address-bus widthbecomes necessary.

According to at least one embodiment, an option of each test function isspecified (identified) by a sub-code (i.e., the first code noted above).The number of bits of a main code (i.e., the second code and the thirdcode noted above) and the number of bits of the sub-code are designed tovary and be different for different functions according to need. Withsuch variation in the number of bits of the main code and the number ofbits of the sub-code, a relatively small number of bits are sufficientto specify a desired number of test functions and a desired number ofoptions. According to at least one embodiment, further, latches(registers) are provided in one-to-one correspondence to test functions.When a main code specifying a test function and a sub-code specifying anoption are entered, the latch specified by decoding the entered maincode stores the value of the entered sub-code. As described above, thenumber of bits of the main code is designed to vary and be different fordifferent functions according to need. Accordingly, the number (i.e.,the first predetermined number) of bits for uniquely specifying a firstlatch and the number (i.e., the third predetermined number) of bits foruniquely specifying a second latch may be different. In such a case, thenumber of decode signal lines for selecting a latch can be reduced withrespect to the latches that can be uniquely identified by a reducednumber of bits.

The advantages of the above-described embodiments can also beappreciated in a system in which a memory and a memory controller arecombined. This is because the number of wire connections connectingbetween a memory and a memory controller should preferably be a minimum.The advantages of the embodiments are also explicitly appreciated in thetesting of semiconductor integrated circuits. When semiconductorintegrated circuits such as memories are tested, a plurality of chipsare concurrently connected to a tester, and the probe pins of the testerare brought in contact with the terminals of these chips that requiresignal input/output. Since the number of probe pins of the tester islimited, it is preferable to have a minimum number of terminals thatrequire signal input/output.

Further, the present invention is not limited to these embodiments, butvarious variations and modifications may be made without departing fromthe scope of the present invention.

1. A semiconductor integrated circuit, comprising: a plurality ofterminals; a first latch configured to, upon being uniquely specified bya first predetermined number of bits that are part of a plurality ofbits entered through the plurality of terminals, store a secondpredetermined number of bits that are at least part of remaining bitsleft after excluding the first predetermined number of bits from theplurality of bits; and a second latch configured to, upon being uniquelyspecified by a third predetermined number of bits that are part of theplurality of bits entered through the plurality of terminals, store afourth predetermined number of bits that are at least part of remainingbits left after excluding the third predetermined number of bits fromthe plurality of bits, wherein the first predetermined number isdifferent from the third predetermined number, and the secondpredetermined number is different from the fourth predetermined number.2. The semiconductor integrated circuit as claimed in claim 1, furthercomprising a core circuit configured to perform an operation responsiveto at least one of the second predetermined number of bits stored in thefirst latch and the fourth predetermined number of bits stored in thesecond latch.
 3. The semiconductor integrated circuit as claimed inclaim 2, wherein the first latch and the second latch constitute a testregister configured to specify a test function for the semiconductorintegrated circuit.
 4. The semiconductor integrated circuit as claimedin claim 3, wherein the core circuit includes a memory cell array, andthe plurality of terminals are address terminals to which addresssignals are supplied to specify memory cells in the memory cell array.5. The semiconductor integrated circuit as claimed in claim 1, whereinthe first predetermined number of bits are part of the thirdpredetermined number of bits.
 6. The semiconductor integrated circuit asclaimed in claim 5, further comprising: a first decoder configured tooutput a first decode signal obtained by decoding the firstpredetermined number of bits; and a second decoder configured to outputa second decode signal obtained by decoding remaining bits left afterexcluding the first predetermined number of bits from the thirdpredetermined number of bits, wherein the first latch is uniquelyidentified by the first decode signal, and the second latch is uniquelyidentified by the first decode signal and the second decode signal.
 7. Amethod of allocating codes to a bit sequence comprised of a plurality ofbits corresponding to a plurality of input terminals of a semiconductorintegrated circuit to cause the semiconductor integrated circuit touniquely identify a function and an option based on codes supplied tothe plurality of input terminals wherein there are one or more optionsseparately for each of a plurality of functions executable by thesemiconductor integrated circuit, the method comprising: determining aminimum number of bits capable of uniquely identifying an option foreach function as a number of bits of a first code that uniquelyidentifies an option for each function; grouping the functions such thatfunctions whose first code has an identical number of bits are groupedtogether; determining a first bit area in the bit sequence for eachgroup for allocation to the first code comprised of a number of bitsspecific to each group; determining a second bit area in the bitsequence for allocation to a second code capable of uniquely identifyinga group; and determining a third bit area allocated to neither the firstbit area nor the second bit area in the bit sequence for allocation to athird code for identifying a function for each group.
 8. The method asclaimed in claim 7, wherein a bit length of the third bit area for agroup having a longest first-code bit length is shorter than a bitlength of the third bit area for another group.
 9. The method as claimedin claim 8, wherein at least one or more bit positions in the bitsequence corresponding to the first bit area for the group having thelongest first-code bit length are allocated to the third bit area inanother group.